// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.2
// 
// Edited by    :  Wang zekun --0430
// Abstract     :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// v1.1 zhangjianyuan
// v1.2 modify logic error line 290/299
//  
// *********************************************************************
`include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// DESCRIPTION
// *******************
// 
// 
//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
module schedule_cpu_interface#(parameter SLAVE_NUM = 38)(
  input  wire       clk                     , 
  input  wire       rst_n                 ,
  //******************************************************************
  //cpu_interface
  //******************************************************************
  //\u961f\u5217&\u7ed3\u70b9\u95e8\u9650
  //cpu interface 
  output reg  [31:0]  np_data_out,
  input  wire [31:0]  np_data_in,
  input  wire [16:0]  np_addr_in,
  input  wire [ 1:0]  np_addr_ctrl, 
  output reg          sch_rd_vld,
  //******************************************************************
  //queue_shedule interface
  //******************************************************************
  //queue_node threshold
  //  enqueue 
  input  wire [ 2:0]  query_CPU_node_minmax_threshold ,  //\u8282\u70b9\u6700\u5c0f\u6700\u5927\u95e8\u9650
  output wire [31:0]  CPU_node_minmax_threshold_data  ,
  input  wire [ 5:0]  query_CPU_queue_max_threshold   ,  //\u961f\u5217\u6700\u5927\u95e8\u9650
  output wire [31:0]  CPU_queue_max_threshold_data    ,
  output reg  [31:0]  CPU_BD_public_length            ,  //BD\u5171\u4eab\u533a\u5927\u5c0f
  //  dequeue
  input  wire [ 2:0]  query_CPU_node_min_threshold  ,
  output wire [31:0]  CPU_node_min_threshold_data   , 


  //rx_tx_frame count
  input  wire [31:0]  rx_frame_cnt_node_0             ,
  input  wire [31:0]  rx_frame_cnt_node_1             ,
  input  wire [31:0]  rx_frame_cnt_node_2             ,
  input  wire [31:0]  rx_frame_cnt_node_3             ,
  input  wire [31:0]  rx_frame_cnt_node_4             ,
  input  wire [31:0]  tx_frame_cnt_node_0             ,
  input  wire [31:0]  tx_frame_cnt_node_1             ,
  input  wire [31:0]  tx_frame_cnt_node_2             ,
  input  wire [31:0]  tx_frame_cnt_node_3             ,
  input  wire [31:0]  tx_frame_cnt_node_4             ,

  //register 
  input  wire [31:0]  ro_reg_np_freeblocknumber_register,
  input  wire [31:0]  ro_reg_np_mac_enqueue_cnt         ,  
  input  wire [31:0]  ro_reg_np_mac_enqueue_fail_cnt    , 
  input  wire [31:0]  ro_reg_np_enqueue_num             ,       
  input  wire [31:0]  ro_reg_np_dequeue_num             ,         
  input  wire [31:0]  ro_reg_np_max_rx_length           ,         
  input  wire [31:0]  ro_reg_np_max_tx_length           ,


  output reg [16:0]  DWRR_en   ,
  output reg [15:0]  WEIGHT7   ,
  output reg [15:0]  WEIGHT6   ,
  output reg [15:0]  WEIGHT5   ,
  output reg [15:0]  WEIGHT4   ,
  output reg [15:0]  WEIGHT3   ,
  output reg [15:0]  WEIGHT2   ,
  output reg [15:0]  WEIGHT1   ,
  output reg [15:0]  WEIGHT0           
  );


//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

reg [16:0]  np_addr_in_d1;
reg [31:0]  np_data_in_d1;
// reg         cpu_reg_rden_d1;
reg         cpu_tx_frame_cnt_rden_d1;
reg         cpu_rx_frame_cnt_rden_d1;
reg         cpu_node_pri_max_thr_rden_d1;
reg         cpu_node_pri_max_min_thr_rden_d1;


//WIRES
//cpu interface
reg        cpu_reg_wren_i;
reg        cpu_reg_rden_i;
//reg        cpu_tx_frame_cnt_wren_i;
reg        cpu_tx_frame_cnt_rden_i;
//reg        cpu_rx_frame_cnt_wren_i;
reg        cpu_rx_frame_cnt_rden_i;
reg        cpu_node_pri_max_thr_rden_i;
reg        cpu_node_pri_max_thr_wren_i;
reg        cpu_node_pri_max_min_thr_wren_i;
reg        cpu_node_pri_max_min_thr_rden_i;

reg [5:0]  queue_address;
reg [2:0]  node_address;
//FIFO
reg [31:0]ram_data_out;
reg [31:0]reg_data_out;
reg ram_rd_en;
reg cpu_reg_rd_vld;
wire        [31:0]queue_tx_frame_cnt_dpram_rdata;
wire        [31:0]queue_rx_frame_cnt_dpram_rdata;
wire        [31:0]queue_node_pri_que_max_thr_dpram_rdata;
wire        [31:0]queue_node_pri_que_max_min_thr_dpram_rdata;
//*********************
//INSTANTCE MODULE
//*********************
schedule_threshold_interface U_schedule_threshold_interface(
   .clk  (clk  ) , 
   .rst_n(rst_n) ,
  //******************************************************************
  //cpu_interface
  //******************************************************************
  //\u961f\u5217&\u7ed3\u70b9\u95e8\u9650
   .queue_node_pri_que_max_thr_dpram_addr     (queue_address                             ),
   .queue_node_pri_que_max_thr_dpram_wen      (cpu_node_pri_max_thr_wren_i               ),
   .queue_node_pri_que_max_thr_dpram_wdata    (np_data_in_d1                         ),
   .queue_node_pri_que_max_thr_dpram_ren      (cpu_node_pri_max_thr_rden_i               ),
   .queue_node_pri_que_max_thr_dpram_rdata    (queue_node_pri_que_max_thr_dpram_rdata    ),
   .queue_node_pri_que_max_min_thr_dpram_addr (node_address                              ),
   .queue_node_pri_que_max_min_thr_dpram_wen  (cpu_node_pri_max_min_thr_wren_i           ),
   .queue_node_pri_que_max_min_thr_dpram_wdata(np_data_in_d1                                ),
   .queue_node_pri_que_max_min_thr_dpram_ren  (cpu_node_pri_max_min_thr_rden_i           ),
   .queue_node_pri_que_max_min_thr_dpram_rdata(queue_node_pri_que_max_min_thr_dpram_rdata),

  //******************************************************************
  //queue_shedule interface
  //******************************************************************

  //  enqueue
   .query_CPU_node_minmax_threshold(query_CPU_node_minmax_threshold),  //\u8282\u70b9\u6700\u5c0f\u6700\u5927\u95e8\u9650
   .CPU_node_minmax_threshold_data (CPU_node_minmax_threshold_data ),
   .query_CPU_queue_max_threshold  (query_CPU_queue_max_threshold  ),  //\u961f\u5217\u6700\u5927\u95e8\u9650
   .CPU_queue_max_threshold_data   (CPU_queue_max_threshold_data   ),

  //  dequeue
   .query_CPU_node_min_threshold(query_CPU_node_min_threshold),
   .CPU_node_min_threshold_data (CPU_node_min_threshold_data )

  );

schedule_frame_cnt_interface U_schedule_frame_cnt_interface(
    .clk  (clk  ) , 
    .rst_n(rst_n) ,
  //******************************************************************
  //cpu_interface
  //******************************************************************
  //\u961f\u5217&\u7ed3\u70b9\u95e8\u9650
    .queue_tx_frame_cnt_dpram_addr  (node_address                     ), 
    //.queue_tx_frame_cnt_dpram_wen   (cpu_tx_frame_cnt_wren_i          ),
    //.queue_tx_frame_cnt_dpram_wdata (np_data_in                       ), 
    .queue_tx_frame_cnt_dpram_ren   (cpu_tx_frame_cnt_rden_i          ),
    .queue_tx_frame_cnt_dpram_rdata (queue_tx_frame_cnt_dpram_rdata   ), 
    .queue_rx_frame_cnt_dpram_addr  (node_address                     ), 
    //.queue_rx_frame_cnt_dpram_wen   (cpu_rx_frame_cnt_wren_i          ),
    //.queue_rx_frame_cnt_dpram_wdata (np_data_in                       ), 
    .queue_rx_frame_cnt_dpram_ren   (cpu_rx_frame_cnt_rden_i          ),
    .queue_rx_frame_cnt_dpram_rdata (queue_rx_frame_cnt_dpram_rdata   ), 

  //******************************************************************
  //queue_shedule interface
  //******************************************************************
    .rx_frame_cnt_node_0            (rx_frame_cnt_node_0              ),
    .rx_frame_cnt_node_1            (rx_frame_cnt_node_1              ),
    .rx_frame_cnt_node_2            (rx_frame_cnt_node_2              ),
    .rx_frame_cnt_node_3            (rx_frame_cnt_node_3              ),
    .rx_frame_cnt_node_4            (rx_frame_cnt_node_4              ),
    .tx_frame_cnt_node_0            (tx_frame_cnt_node_0              ),
    .tx_frame_cnt_node_1            (tx_frame_cnt_node_1              ),
    .tx_frame_cnt_node_2            (tx_frame_cnt_node_2              ),
    .tx_frame_cnt_node_3            (tx_frame_cnt_node_3              ),
    .tx_frame_cnt_node_4            (tx_frame_cnt_node_4              )
  );

//*********************
//MAIN CORE
//*********************
//====================================================================
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        cpu_reg_wren_i <= 1'b0;
    else if(np_addr_ctrl[1])
        cpu_reg_wren_i <= !(|np_addr_in[16:10]);
    else
        cpu_reg_wren_i <= 1'b0;
end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        cpu_reg_rden_i <= 1'b0;
    else if(np_addr_ctrl[0])
        cpu_reg_rden_i <= !(|np_addr_in[16:10]);
    else
        cpu_reg_rden_i <= 1'b0;
end

//-------------------------------------------------------------
wire cpu_node_pri_max_thr_en;
assign cpu_node_pri_max_thr_en = np_addr_in[16:6]==`NODE_PRI_MAX_THR_BASE_ADDR;
always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    cpu_node_pri_max_thr_wren_i <= 1'b0;
  else if(np_addr_ctrl[1] && cpu_node_pri_max_thr_en)
    cpu_node_pri_max_thr_wren_i <= 1'b1;
  else
    cpu_node_pri_max_thr_wren_i <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    cpu_node_pri_max_thr_rden_i <= 1'b0;
  else if(np_addr_ctrl[0] && cpu_node_pri_max_thr_en)
    cpu_node_pri_max_thr_rden_i <= 1'b1;
  else
    cpu_node_pri_max_thr_rden_i <= 1'b0;
end
//-------------------------------------------------------------
wire cpu_node_pri_max_min_thr_en;
assign cpu_node_pri_max_min_thr_en = np_addr_in[16:6]==`NODE_PRI_MAX_MIN_THR_BASE_ADDR;
always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    cpu_node_pri_max_min_thr_wren_i <= 1'b0;
  else if(np_addr_ctrl[1] && cpu_node_pri_max_min_thr_en)
    cpu_node_pri_max_min_thr_wren_i <= 1'b1;
  else
    cpu_node_pri_max_min_thr_wren_i <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    cpu_node_pri_max_min_thr_rden_i <= 1'b0;
  else if(np_addr_ctrl[0] && cpu_node_pri_max_min_thr_en)
    cpu_node_pri_max_min_thr_rden_i <= 1'b1;
  else
    cpu_node_pri_max_min_thr_rden_i <= 1'b0;
end
//-------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    queue_address <= 6'b0;
  else if(np_addr_in[16:6]>=`NODE_PRI_MAX_THR_BASE_ADDR && np_addr_in[16:6]<`NODE_PRI_MAX_MIN_THR_BASE_ADDR)
    queue_address <= np_addr_in[5:0];
end
//-------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    cpu_tx_frame_cnt_rden_i <= 1'b0;
  else if(np_addr_ctrl[0] && np_addr_in[16:3]>=`TX_FRM_CNT_BASE_ADDR && np_addr_in[16:3]<`RX_FRM_CNT_BASE_ADDR)
    cpu_tx_frame_cnt_rden_i <= 1'b1;
  else
    cpu_tx_frame_cnt_rden_i <= 1'b0;
end
//-------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    cpu_rx_frame_cnt_rden_i <= 1'b0;
  else if(np_addr_ctrl[0] && np_addr_in[16:3]>=`RX_FRM_CNT_BASE_ADDR && np_addr_in[16:6]<`NODE_PRI_MAX_THR_BASE_ADDR)
    cpu_rx_frame_cnt_rden_i <= 1'b1;
  else
    cpu_rx_frame_cnt_rden_i <= 1'b0;
end
//-------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
    node_address <= 3'b0;
  else if((np_addr_in[16:6]>=`NODE_PRI_MAX_MIN_THR_BASE_ADDR && np_addr_in[16:10]<`XLPCS_BASE_ADDR)||(np_addr_in[16:3]>=`TX_FRM_CNT_BASE_ADDR && np_addr_in[16:6]<`NODE_PRI_MAX_THR_BASE_ADDR))
    node_address <= np_addr_in[2:0];
end
//=========================================================================

// assign    cpu_node_pri_max_thr_wren_i     = np_addr_ctrl[3];         
// assign    cpu_node_pri_max_thr_rden_i     = np_addr_ctrl[2];
// assign    cpu_node_pri_max_min_thr_wren_i = np_addr_ctrl[1];         
// assign    cpu_node_pri_max_min_thr_rden_i = np_addr_ctrl[0];
//assign    cpu_tx_frame_cnt_wren_i         = np_addr_ctrl[7];
// assign    cpu_tx_frame_cnt_rden_i         = np_addr_ctrl[6]; 
//assign    cpu_rx_frame_cnt_wren_i         = np_addr_ctrl[5];
// assign    cpu_rx_frame_cnt_rden_i         = np_addr_ctrl[4];   

// assign    node_address                    = np_addr_in[2:0];
// assign    queue_address                   = np_addr_in[5:0];

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    np_addr_in_d1                     <= 'b0 ;
    np_data_in_d1                     <= 'b0 ;
    // cpu_reg_rden_d1                   <= 'b0 ;
    cpu_tx_frame_cnt_rden_d1          <= 'b0 ;
    cpu_rx_frame_cnt_rden_d1          <= 'b0 ;
    cpu_node_pri_max_thr_rden_d1      <= 'b0 ;
    cpu_node_pri_max_min_thr_rden_d1  <= 'b0 ;
  end
  else begin
    np_addr_in_d1                     <= np_addr_in                        ;
    np_data_in_d1                     <= np_data_in;
    // cpu_reg_rden_d1                   <= cpu_reg_rden_i                    ;
    cpu_tx_frame_cnt_rden_d1          <= cpu_tx_frame_cnt_rden_i           ;
    cpu_rx_frame_cnt_rden_d1          <= cpu_rx_frame_cnt_rden_i           ;
    cpu_node_pri_max_thr_rden_d1      <= cpu_node_pri_max_thr_rden_i       ;
    cpu_node_pri_max_min_thr_rden_d1  <= cpu_node_pri_max_min_thr_rden_i   ;
  end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    CPU_BD_public_length   <= 32'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_CPU_BD_PUBLIC_LENGTH)) begin
    CPU_BD_public_length   <= np_data_in_d1;
  end
  // else begin
  //   CPU_BD_public_length   <= CPU_BD_public_length;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    DWRR_en   <= 17'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_EN)) begin
    DWRR_en   <= np_data_in_d1[16:0];
  end
  // else begin
  //   DWRR_en   <= DWRR_en;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT0   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT0)) begin
    WEIGHT0   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT0   <= WEIGHT0;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT1   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT1)) begin
    WEIGHT1   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT1   <= WEIGHT1;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT2   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT2)) begin
    WEIGHT2   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT2   <= WEIGHT2;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT3   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT3)) begin
    WEIGHT3   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT3   <= WEIGHT3;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT4   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT4)) begin
    WEIGHT4   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT4   <= WEIGHT4;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT5   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT5)) begin
    WEIGHT5   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT5   <= WEIGHT5;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT6   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT6)) begin
    WEIGHT6   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT6   <= WEIGHT6;
  // end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    WEIGHT7   <= 16'b0 ;
  end
  else if(cpu_reg_wren_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT7)) begin
    WEIGHT7   <= np_data_in_d1[15:0];
  end
  // else begin
  //   WEIGHT7   <= WEIGHT7;
  // end
end


always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    ram_data_out     <= 32'b0 ;
    ram_rd_en <= 1'b0;
  end
  else if(cpu_node_pri_max_thr_rden_d1) begin
    ram_data_out     <= queue_node_pri_que_max_thr_dpram_rdata;
    ram_rd_en        <= 1'b1  ;
  end
  else if(cpu_node_pri_max_min_thr_rden_d1) begin
    ram_data_out     <= queue_node_pri_que_max_min_thr_dpram_rdata;
    ram_rd_en        <= 1'b1  ;
  end
  else if(cpu_tx_frame_cnt_rden_d1) begin
    ram_data_out     <= queue_tx_frame_cnt_dpram_rdata;
    ram_rd_en <= 1'b1;
  end
  else if(cpu_rx_frame_cnt_rden_d1) begin
    ram_data_out     <= queue_rx_frame_cnt_dpram_rdata;    
    ram_rd_en <= 1'b1;
  end
  else begin
    // ram_data_out     <=  ram_data_out;
    ram_rd_en <= 1'b0;
  end
end
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    // reset
    reg_data_out     <= 32'b0 ;
    cpu_reg_rd_vld <= 1'b0;
  end  
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_FREEBLOCKNUMBER_REGISTER)) begin
    reg_data_out     <= ro_reg_np_freeblocknumber_register;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_MAC_ENQUEUE_CNT)) begin
    reg_data_out     <= ro_reg_np_mac_enqueue_cnt;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_MAC_ENQUEUE_FAIL_CNT)) begin
    reg_data_out     <= ro_reg_np_mac_enqueue_fail_cnt;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_ENQUEUE_NUM)) begin
    reg_data_out     <= ro_reg_np_enqueue_num;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DEQUEUE_NUM)) begin
    reg_data_out     <= ro_reg_np_dequeue_num;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_MAX_RX_LENGTH)) begin
    reg_data_out     <= ro_reg_np_max_rx_length;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_MAX_TX_LENGTH)) begin
    reg_data_out     <= ro_reg_np_max_tx_length;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_CPU_BD_PUBLIC_LENGTH)) begin
    reg_data_out     <= CPU_BD_public_length;
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_EN)) begin
    reg_data_out     <=  {17'b0,DWRR_en};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT0)) begin
    reg_data_out     <=  {16'b0,WEIGHT0};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT1)) begin
    reg_data_out     <=  {16'b0,WEIGHT1};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT2)) begin
    reg_data_out     <=  {16'b0,WEIGHT2};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT3)) begin
    reg_data_out     <=  {16'b0,WEIGHT3};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT4)) begin
    reg_data_out     <=  {16'b0,WEIGHT4};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT5)) begin
    reg_data_out     <=  {16'b0,WEIGHT5};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT6)) begin
    reg_data_out     <=  {16'b0,WEIGHT6};
    cpu_reg_rd_vld <= 1'b1;
  end
  else if(cpu_reg_rden_i && (np_addr_in_d1==`ADDR_DWRR_WEIGHT7)) begin
    reg_data_out     <=  {16'b0,WEIGHT7};
    cpu_reg_rd_vld <= 1'b1;
  end
  else begin
    // reg_data_out     <=  reg_data_out;
    cpu_reg_rd_vld <= 1'b0;
  end
end


always @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    np_data_out <= 32'b0;
    sch_rd_vld <= 1'b0; 
  end else if(ram_rd_en) begin
    np_data_out <= ram_data_out;
    sch_rd_vld <= 1'b1; 
  end else if(cpu_reg_rd_vld) begin
    np_data_out <= reg_data_out;
    sch_rd_vld <= 1'b1; 
  end else begin
    np_data_out <= np_data_out;
    sch_rd_vld <= 1'b0; 
  end
end

     
endmodule

